The present invention relates to a semiconductor device with a wiring structure having interlayer-insulating films each made of an insulating film with a low relative dielectric constant, especially a porous film, and a method of producing this type of semiconductor device.
Two major factors in delay in operation speed for large-scale integrated circuits are delay in operation of transistors themselves and delay (RC delay) in signals propagating through wirings.
Miniaturization and high integration of wirings and devices affects recent advancement in semiconductor fabrication process highlight the effects of RC delay rather than delay in operation of transistors themselves. Protection against RC delay promotes development of wiring materials of a low resistivity and insulating films of a low relative dielectric constant (called low-dielectric-constant insulating films hereinafter).
One recent wiring material is copper (Cu) with resistivity lower than a known wiring material aluminum (Al). Copper requires a relatively high vapor pressure in etching, and hence hard to be processed by reactive ion etching with chloride gas at a low vapor pressure. It is thus processed by damascene in wiring formation.
Developed for low-dielectric-constant insulating films is application of organic material-applied insulating films of a low relative dielectric constant in the range from about 2.5 to 2.8 such as methyl siloxane to multi-layered wiring processes.
Also there are developed porous insulating films having many nanometer-size pores. Porous insulating films can have relative dielectric constant of 2.5 or smaller by lowering the film density with pore-number adjustments. Use of porous insulating films as interlayer-insulating films in semiconductors with a multi-layered wiring structure protects against RC delays.
Organic material-applied insulating films having a low relative dielectric constant are, however, could suffer degradation or increase in hygroscopic property due to O2 gas-ashing in resist-peeling process, when used as interlayer-insulating films in multi-layered wiring process. Insulating films having a low relative dielectric constant could also suffer clucks in etching process.
Moreover, porous insulating films could have a high relative dielectric constant due to permeation of etching gas and chemical solution into pores generated in the porous insulating films, and suffer clucks or peeling-off due to discharging of the etching gas and chemical solution in post-thermal processes.
A wiring-layer structure having interlayer-insulating films may have several types in accordance with a width of each of several wiring layers and a distance between adjacent wiring layers. Such a wiring-layer structure has a tendency to have a small width for each interlayer-insulating film provided laterally as the width of each wiring layer becomes small. This tendency is used for wiring-layer structure miniaturization.
One of the problems for such wiring-layer structure miniaturization is RC delay due to increase in parasitic capacitance between wiring layers.
Several techniques have been proposed for decreasing parasitic capacitance between wiring layers to prevent decrease in signal propagation speed and generation of cross-talks between wiring layers with different relative dielectric constants for interlayer-insulating films having a relatively big inter-wiring distance and those having a relatively small inter-wiring distance.
Japanese Patent No. 2910713 discloses a wiring-layer structure having interlayer-insulating films of high mechanical strength and also high moisture resistance in a wide wiring-interval region and those of low relative dielectric constant in a narrow wiring-interval region.
Japanese Unexamined Patent Publication No. 2000-49228 discloses a dual-damascene wiring-layer structure having a first wide region 240 between metallized portions and a second narrow region between metallized portions, made of a dielectric material having a low dielectric constant.
Neither prior art, however, discloses insulating-film structures at different layer stages of a multi-layered wiring structure.
In detail, the latter prior art does not discuss any multi-layered wiring structure. The former discloses a multi-layered wiring structure in FIGS. 1, 5 and 7, for example, however, only for production of a wide first interlayer-insulating film 4 and a narrow second interlayer-insulating film 5 at the same layer stage. In other words, no discussion is made in the former prior art on a relation between the wiring layers for a lower-stage wiring 3 and an upper-stage wiring 10 and also production of a lower-stage first interlayer-insulating film 4 and the corresponding upper-stage fourth interlayer-insulating film 11 and their relative dielectric constants.